This invention relates to nonvolatile memory arrays, such as electrically-erasable, electrically-programmable, read-only-memory (EEPROM) arrays, and more particularly to a method for programming memory cells in such arrays in a manner that will not unintentionally de-program memory cells that have been previously programmed and that will not unintentionally program memory cells that are deselected.
EEPROMs, or electrically-erasable, electrically-programmable, read-only-memories, are field-effect devices having a floating-gate-type structure. An EEPROM floating gate is programmed by applying proper voltages to the source, drain and control gate of each cell, causing current to flow from a source or source-line through the gate insulator to the floating gate. Flash EEPROMs are EEPROMS that may be erased in bulk or in blocks instead of each cell being erased individually.
To reduce cell size and cost of manufacture, an EEPROM cell integrating a remotely located tunnelling area with a floating-gate transistor has recently been devised. The structural characteristics of the cell and its method of manufacture have been disclosed in U.S. patent application Ser. No. 07/219,529. This Application describes and claims a novel method for programming cells of the type disclosed as well as other types of non-volatile memory cells.
Prior-art programming procedures typically require that a preselected high voltage be placed on a selected wordline conductor connected to each memory cell in a row. Each wordline conductor is insulated from and disposed adjacent to a floating gate conductor of each cell in the respective row. Also, as in prior-art procedures, a preselected low programming voltage that is substantially less positive than the first programming voltage is placed on a selected one of a plurality of elongated semiconductor column lines formed at an angle to the wordlines, each memory cell in a column of memory cells being connected to a column line. In the selected memory cell at the intersection of the selected wordline conductor and the selected column line, electrons flow through a programming window insulator from the selected column line to the floating gate, programming the memory cell.
During the programming operation, previously programmed memory cells tend to become de-programmed. While programming methods have been disclosed in which voltages are applied to prevent such unintentional de-programming, those methods do not provide the necessary timing sequences for applying those voltages or provide the relative magnitudes of those voltages. The timing sequences are critical because the resistances and capacitances associated with wordlines and circuitry connected thereto generally differ from the resistances and capacitances associated with column lines and circuitry connected thereto. Furthermore, the resistances and capacitances of wordlines and column lines and circuitry connected thereto differ among themselves because of the different-length interconnections. Because the resistances and capacitances differ, the time constants associated with voltages applied to those wordlines and column lines differ. There is a need for an application sequence for voltages that will avoid unintentional de-programming of previously programmed cells, as well as avoid unintentional programming of deselected cells.